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document no. e1379e20 (ver. 2.0) date published december 2008 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2008 preliminary data sheet 1g bits ddr sdram wtr (wide temperature ra nge), low power function edd10163abh-ls (64m words 16 bits) specifications ? density: 1g bits ? organization: 16m words 16 bits 4 banks ? package: 60-ball fbga ? lead-free (rohs compliant) and halogen-free ? power supply: vdd, vddq = 1.8v 0.1v ? data rate: 333m bps/266mbps (max.) ? 2kb page size ? row address: a0 to a13 ? column address: a0 to a9 ? four internal banks for concurrent operation ? interface: lvcmos ? burst lengths (bl): 2, 4, 8, 16 ? burst type (bt): ? sequential (2, 4, 8, 16) ? interleave (2, 4, 8, 16) ? /cas latency (cl): 3 ? precharge: auto precharge option for each burst access ? driver strength: normal, 1/2, 1/4, 1/8 ? refresh: auto-refresh, self-refresh ? refresh cycles: 8192 cycles/64ms ? average refresh period: 7.8 s ? operating ambient temperature range ? ta = ? 25 c to +85 c features ? dll is not implemented ? low power consumption ? partial array self-refresh (pasr) ? auto temperature compensated self-refresh (atcsr) by built-in temperature sensor ? deep power-down mode ? double-data-rate architecture; two data transfers per one clock cycle ? the high-speed data transfer is realized by the 2 bits prefetch pipelined architecture ? bi-directional data strobe (dqs) is transmitted /received with data for capt uring data at the receiver. ? data inputs, outputs, and dm are synchronized with dqs ? dqs is edge-aligned with data for reads; center- aligned with data for writes ? differential clock inputs (ck and /ck) ? commands entered on each positive ck edge: data and data mask referenced to both edges of dqs ? data mask (dm) for write data ? burst termination by burst stop command and precharge command ? wide temperature range ? ta = ? 25 c to +85 c
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 2 ordering information part number die revision organization (words bits) internal banks data rate mbps (max.) /cas latency package EDD10163ABH-6DLS-F a 64m 16 4 333 3 60-ball fbga edd10163abh-7fls-f 266 part number elpida memory density / bank 10: 1gb / 4-bank organization 16: x16 power supply, interface 3: 1.8v, lvcmos, low power function die rev. package bh: fbga speed 6d: ddr333 (3-4-3) 7f: ddr266 (3-3-3) product family d: ddr sdram type d: monolithic device e d d 10 16 3 a bh - 6d ls - f environment code f: lead free (rohs compliant) and halogen free spec detail ls: wtr ( ? 25 c to +85 c) & low power
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 3 pin configurations /xxx indicate active low signal. a b c d e f g h j 123 789 (top view) k vss dq15 vssq vddq dq0 vdd dq14 dq13 vddq vssq dq2 dq1 dq12 dq11 vssq vddq dq4 dq3 dq10 dq9 vddq vssq dq6 dq5 dq8 vssq vddq ldqs dq7 udqs nc udm vdd ldm a13 vss ck cke /cas /ras /w e ck a12 a11 a9 ba0 ba1 / cs a8 a7 a6 a0 a1 a10 vss a5 a4 a3 a2 vdd 60-ball fbga / pin name function pin name function a0 to a13 address inputs ck clock input ba0, ba1 bank select address /ck differential clock input dq0 to dq15 data-input/output cke clock enable udqs, ldqs input and output data strobe vdd power for internal circuit /cs chip select vss ground for internal circuit /ras row address strobe vddq power for dq circuit /cas column address strobe vssq ground for dq circuit /we write enable nc no connection udm, ldm input mask
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 4 contents specifications................................................................................................................. ................................1 features....................................................................................................................... ..................................1 ordering in format ion........................................................................................................... ...........................2 part nu mber .................................................................................................................... ..............................2 pin config urations ............................................................................................................. ............................3 electrical sp ecifications...................................................................................................... ...........................5 block diagram .................................................................................................................. ...........................11 pin function................................................................................................................... ..............................12 command oper ation .............................................................................................................. .....................14 simplified st ate di agram ....................................................................................................... ......................20 operation of t he ddr s dram ..................................................................................................... ...............21 timing wave forms............................................................................................................... ........................45 package dr awing ................................................................................................................ ........................56 recommended solder ing conditions............................................................................................... ...........57
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 5 electrical specifications ? all voltages are referenced to vss (gnd). ? after power up, wait more than 200 s and then, execute power on sequence and cbr (auto) refresh before proper device operation is achieved. absolute maximum ratings parameter symbol rating unit note voltage on any pin relative to vss vt ? 0.5 to +2.3 v supply voltage relative to vss vdd ? 0.5 to +2.3 v short circuit output current ios 50 ma power dissipation pd 1.0 w operating ambient temperature ta ? 25 to +85 c storage temperature tstg ? 55 to +125 c caution exposing the device to stress above those listed in absolute maximum ratings could cause permanent damage. the device is not meant to be operated under conditions outside the limits described in the operational section of this speci fication. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (ta = ? 25 c to +85 c) parameter pins symbol min typ. max unit notes supply voltage vdd, vddq 1.7 1.8 1.9 v 1 vss, vssq 0 0 0 v input high voltage all other input vih 0.8 vddq ? vddq + 0.3 v input low voltage pins vil ? 0.3 ? 0.2 vddq v dc input voltage level ck, /ck vin (dc) ? 0.3 ? vddq + 0.3 v ac input differential cross point voltage vix 0.4 vddq 0.5 vddq 0.6 vddq v 6 dc input differential voltage vid (dc) 0.4 vddq ? vddq + 0.6 v 5 ac input differential voltage vid (ac) 0.6 vddq ? vddq + 0.6 v 5 dc input high voltage dq, dm, dqs vihd (dc) 0.7 vddq ? vddq + 0.3 v dc input low voltage vild (dc) ? 0.3 ? 0.3 vddq v ac input high voltage vihd (ac) 0.8 vddq ? vddq + 0.3 v ac input low voltage vild (ac) ? 0.3 ? 0.2 vddq v notes: 1. vddq must be equal to vdd. 2. vih (max.) = 2.3v (pulse width 5ns). 3. vil (min.) = ? 0.5v (pulse width 5ns). 4. all voltage referred to vss an d vssq must be same potential. 5. vid (dc) and vid (ac) are the magnitude of the difference between t he input level on ck and the input level on /ck. 6. the value of vix is expected to be 0.5 vddq and must track variations in the dc level of the same.
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 6 dc characteristics 1 (ta = ? 25 c to +85 c, vdd and vddq = 1.8v 0.1v, vss and vssq = 0v) parameter symbol grade max. unit test condition notes operating current idd1 -6dls -7fls 70 60 ma burst length = 2 trc trc (min.), io = 0ma, one bank active 1 standby current in power-down idd2p 1.0 ma cke vil (max.), tck = tck (min.) standby current in power-down (input signal stable) idd2ps 0.8 ma cke vil (max.), tck = standby current in non power-down idd2n -6dls -7fls 5.0 4.0 ma cke vih (min.), tck = tck (min.), /cs vih (min.), input signals are changed one time during 2tck. standby current in non power-down (input signal stable) idd2ns 2.0 ma cke vih (min.), tck = , input signals are stable. active standby current in power-down idd3p 3.5 ma cke vil (max.), tck = tck (min.) active standby current in power-down (input signal stable) idd3ps 3.0 ma cke vil (max.), tck = active standby current in non power- down idd3n 10 ma cke vih (min.), tck = tck (min.), /cs vih (min.), input signals are changed one time during 2tck. active standby current in non power- down (input signal stable) idd3ns 7.0 ma cke vih (min.), tck = , input signals are stable. burst operating current idd4 -6dls -7fls 130 110 ma burst length = 4 tck tck (min.), iout = 0ma, all banks active 2 refresh current idd5 110 ma trfc trfc (min.) 3 standby current in deep power-down mode idd7 10 a cke 0.2v advanced data retention current (ta = ? 25 c to +85 c, vdd and vddq = 1.8v 0.1v, vss and vssq = 0v) parameter symbol grade typ. max. unit condition notes advanced data retention current (self-refresh current) pasr="000" (full) idd6 ? 500 a ? 25 c ta +40 c cke 0.2v pasr="001" (2bk) ? 440 a pasr="010" (1bk) ? 400 a pasr="000" (full) idd6 ? 900 a +40 c < ta +70 c pasr="001" (2bk) ? 600 a cke 0.2v pasr="010" (1bk) ? 480 a pasr="000" (full) idd6 ? 1200 a +70 c < ta +85 c pasr="001" (2bk) ? 800 a cke 0.2v pasr="010" (1bk) ? 600 a
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 7 notes: 1. idd1 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, idd1 is measured on conditi on that addresses are changed only one time during tck (min.). 2. idd4 depends on output loading and cycle rates. specified values are obtained with the output open. in addition to this, idd4 is measured on conditi on that addresses are changed only one time during tck (min.). 3. idd5 is measured on condit ion that addresses are changed only one time during tck (min.). dc characteristics 2 (ta = ? 25 c to +85 c, vdd and vddq = 1.8v 0.1v, vss and vssq = 0v) parameter symbol min. max. unit test condition notes input leakage current ili ? 2.0 2.0 a 0 vin vddq output leakage current ilo ? 1.5 1.5 a 0 vout vddq, dq = disable output high voltage voh 0.9 vddq ? v ioh = ? 0.1ma output low voltage vol ? 0.1 vddq v iol = 0.1ma pin capacitance (ta = +25c, vdd and vddq = 1.8v 0.1v) parameter symbol pins min. typ. max. unit notes input capacitance ci1 ck, /ck 1.5 ? 3.5 pf 1 ci2 all other input-only pins 1.5 ? 3.0 pf 1 delta input capacitance cdi1 ck, /ck ? ? 0.25 pf 1 cdi2 all other input-only pins ? ? 1.0 pf 1 data input/output capacitance ci/o dq, dm, dqs 2.0 ? 4.5 pf 1, 2 delta input/output capacitance cdio dq, dm, dqs ? ? 1.0 pf 1 notes: 1. these parameters are measured on conditions: f = 100mhz, vout = vddq/2, ? vout = 0.2v, ta = +25 c. 2. dout circuits are disabled.
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 8 ac characteristics (ta = ? 25 c to +85 c, vdd and vddq = 1.8v 0.1v, vss and vssq = 0v) -6dls -7fls parameter symbol min. max. min. max. unit notes clock cycle time tck 6.0 ? 7.5 ? ns ck high-level width tch 0.45 0.55 0.45 0.55 tck ck low-level width tcl 0.45 0.55 0.45 0.55 tck ck half period thp min. (tch, tcl) ? min. (tch, tcl) ? tck dq output access time from ck, /ck tac 2.0 5.0 2.0 6.0 ns 2, 8 dqs-in cycle time tdsc 0.9 1.1 0.9 1.1 tck dqs output access time from ck, /ck tdqsck 2.0 5.0 2.0 6.0 ns 2, 8 dq-out high-impedance time from ck, /ck thz ? 5.5 ? 6.0 ns 5, 8 dq-out low-impedance time from ck, /ck tlz 1.0 ? 1.0 ? ns 6, 8 dqs to dq skew tdqsq ? 0.5 ? 0.6 ns 3 dq/dqs output hold time from dqs tqh thp ? tqhs ? thp ? tqhs ? ns 4 data hold skew factor tqhs ? 0.65 ? 0.75 ns dq and dm input setup time tds 0.6 ? 0.8 ? ns 3 dq and dm input hold time tdh 0.6 ? 0.8 ? ns 3 dq and dm input pulse width tdipw 1.75 ? 1.75 ? ns read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck write preamble setup time twpres 0 ? 0 ? ns write preamble twpre 0.25 ? 0.25 ? tck write postamble twpst 0.4 0.6 0.4 0.6 tck 7 write command to first dqs latching transition tdqss 0.75 1.25 0.75 1.25 tck dqs falling edge to ck setup time tdss 0.2 ? 0.2 ? tck dqs falling edge hold time from ck tdsh 0.2 ? 0.2 ? tck dqs input high pulse width tdqsh 0.35 ? 0.35 ? tck dqs input low pulse width tdqsl 0.35 ? 0.35 ? tck address and control input setup time tis 1.1 ? 1.3 ? ns 3 address and control input hold time tih 1.1 ? 1.3 ? ns 3 address and control input pulse width tipw 2.7 ? 3.0 ? ns 3 mode register set command cycle time tmrd 2 ? 2 ? tck active to precharge command period tras 42 120000 45 120000 ns active to active/auto-refresh command period trc 60 ? 75 ? ns auto-refresh to active/auto-refresh command period trfc 138 ? 138 ? ns active to read/write delay trcd 22.5 ? 22.5 ? ns precharge to active command period trp 18 ? 22.5 ? ns column address to column address delay tccd 1 ? 1 ? tck active to active command period trrd 12 ? 15 ? ns write recovery time twr 15 ? 15 ? ns
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 9 -6dls -7fls parameter symbol min. max. min. max. unit notes autoprecharge write recovery and precharge time tdal twr + trp ? twr + trp ? ns self-refresh exit period tsrex 200 ? 200 ? ns internal write to read command delay twtr 2 ? 1 ? tck average periodic refresh interv al tref ? 7.8 ? 7.8 s notes: 1. on all ac measurements, we assume the te st conditions shown in ?test conditions? and full driver strength is assumed for the output load, that is both a6 and a5 of emrs is set to be ?l?. 2. this parameter defines the signal transition delay from the cr oss point of ck and /ck. the signal transition is defined to occur when the signal level crossing vddq/2. 3. the timing reference level is vddq/2. 4. output valid window is defined to be the period between two successi ve transition of data out signals. the signal transition is defined to occur when the signal level crossing vddq/2. 5. thz is defined as dout transit ion delay from low-z to high-z at t he end of read burst operation. the timing reference is cross point of ck and /ck. this parameter is not referred to a specific dout voltage level, but specify when the device output stops driving. 6. tlz is defined as dout transition delay from hi gh-z to low-z at the beginni ng of read operation. this parameter is not referred to a s pecific dout voltage leve l, but specify when the device output begins driving. 7. the transition from low-z to high-z is defined to o ccur when the device output st ops driving. a specific reference voltage to judge this transition is not given. 8. tac, tdqsck, thz and tlz are specified with 15pf bus loading conditio n. test conditions parameter symbol value unit note input high voltage vih (ac) 1.6 v input low voltage vil (ac) 0.2 v input differential voltage, ck and /ck inputs vid (ac) 1.4 v input differential cross point voltage, ck and /ck inputs vix (ac) vddq/2 with vdd=vddq v input signal slew rate slew 1 v/ns output load cl 15 pf tck tch tlz tac tcl /ck ck vid vix dqout (dqout) q1 q2 vddq/2 t slew rate = t (v ih ? v il ) vih (=1.6v) vil (=0.2v) test condition (wave form and timing reference) dq cl output load
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 10 timing parameter measured in clock cycle number of clock cycle tck 6.0ns 7.5ns parameter symbol min. max. min. max. unit write to pre-charge command delay (same bank) twpd 4 + bl/2 ? 3 + bl/2 ? tck read to pre-charge command delay (same bank) trpd bl/2 ? bl/2 ? tck write to read command delay (to input all data) twrd 3 + bl/2 ? 2 + bl/2 ? tck burst stop command to write command delay (cl = 3) tbstw 3 ? 3 ? tck burst stop command to dq high-z (cl = 3) tbstz 3 ? 3 ? tck read command to write command delay (to output all data) (cl = 3) trwd 3 + bl/2 ? 3 + bl/2 ? tck pre-charge command to high-z (cl = 3) thzp 3 ? 3 ? tck write command to data in latency twcd 1 ? 1 ? tck write recovery twr 3 ? 2 ? tck dm to data in latency tdmd 0 ? 0 ? tck mode register set command cycle time tmrd 2 ? 2 ? tck self-refresh exit to non-column command tsrex 34 ? 27 ? tck auto-refresh period trfc 23 ? 19 ? tck power-down entry tpden 2 ? 2 ? tck power-down exit to command input tpdex 1 ? 1 ? tck cke minimum pulse width tcke 2 ? 2 ? tck
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 11 block diagram address, ba0, ba1 /cs /ras /cas /we command decoder input & output buffer latch circuit data control circuit column decoder row decoder memory cell array bank 0 sense amp. bank 1 bank 2 bank 3 control logic column address buffer and burst counter row address buffer and refresh counter mode register clock generator dq ck /ck cke dqs dm
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 12 pin function ck, /ck (input pins) the ck and the /ck are the master clock inputs. all in puts except dms, dqss and dqs are referred to the cross point of the ck rising edge and the /c k falling edge. when a read operation, dqss and dqs are referred to the cross point of the ck and the /ck. when a write operation, dms and dqs are re ferred to the cross point of the dqs and the vddq/2 level. dqss for write operation are referr ed to the cross point of the ck and the /ck. the other input signals are referred at ck rising edge. /cs (input pin) when /cs is low, commands and data can be input. when /cs is high, all inputs are ignored. however, internal operations (bank active, burst operations, etc.) are held. /ras, /cas, and /we (input pins) these pins define operating commands (re ad, write, etc.) depending on the comb inations of their voltage levels. see "command operation". a0 to a13 (input pins) row address (ax0 to ax13) is determined by the a0 to the a13 level at the cross point of the ck rising edge and the /ck falling edge in a bank active command cycle. column address is loaded at the cross point of the ck rising edge and the /ck falling edge in a read or a write command cycle (see ?address pins table?). this column address becomes the starting addre ss of a burst operation. [address pins table] address (a0 to a13) part number page size organization row address column address edd10163abh 2kb 16 bits ax0 to ax13 ay0 to ay9 a10 (ap) (input pin) a10 defines the precharge mode when a precharge command, a read command or a write command is issued. if a10 = high when a precharge command is issued, all banks are precharged. if a10 = low when a precharge command is issued, only the bank that is selected by ba1/ba0 is precharged. if a10 = high when read or write command, auto precharge function is enabled. ba0 and ba1 (input pins) ba0 and ba1 are bank select signals (ba). the memory arra y is divided into bank 0, bank 1, bank 2 and bank 3. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil.
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 13 cke (input pin) cke controls power-down mode, self-refresh function and deep power-down function with other command inputs. the cke level must be kept for 2 clocks at least, that is, if cke changes at the cross poi nt of the ck rising edge and the /ck falling edge with proper setup time tis, by the ne xt ck rising edge cke level must be kept with proper hold time tih. dq0 to dq15 (input/output pins) data are input to and output from these pins. udqs and ldqs (input and output pin): dqs provides the read data st robes (as output) and the write data strobes (as input). each dqs pin corresponds to eight dq pins, respectively (see dqs and dm correspondence table). udm and ldm (input pin) dm is the reference signals of the dat a input mask function. dm is sampled at the cross point of dqs and vddq/2. when dm = high, the data input at the same timing are masked while the in ternal burst counter will be counting up. each dm pin corresponds to eight dq pins, respectively (see dqs and dm correspondence table). [dqs and dm correspondence table] part number organization dqs data mask dqs edd10163abh 16 bits ldqs ldm dq0 to dq7 udqs udm dq8 to dq15 vdd, vss, vddq, vssq (power supply) vdd and vss are power supply pins for internal circuits . vddq and vssq are power supply pins for the output buffers. vdd must be equal to vddq.
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 14 command operation command truth table the ddr sdram recognizes the following commands spec ified by the /cs, /ras, /cas, /we and address pins. cke command symbol n ? 1 n /cs /ras /cas /we ba1 ba0 ap address ignore command desl h h h no operation nop h h l h h h burst stop command bst h h l h h l column address and read command read h h l h l h v v l v read with auto precharge reada h h l h l h v v h v column address and write command writ h h l h l l v v l v write with auto precharge writa h h l h l l v v h v row address strobe and bank active act h h l l h h v v v v precharge select bank pre h h l l h l v v l precharge all bank pall h h l l h l h refresh ref h h l l l h self h l l l l h mode register set mrs h h l l l l l l l v emrs h h l l l l h l l v remark: h: vih. l: vil. : don?t care v: valid address input note: the cke level must be kept for 1 ck cycle at least. ignore command [desl] when /cs is high at the cross point of the ck rising edge and the vddq/2 level, all input signals are neglected and internal state is held. no operation [nop] as long as this command is input at the cross point of the ck rising edge and the vddq/2 level, address and data input are neglected and internal state is held. burst stop command [bst] this command stops a current burst operation. column address strobe and read command [read] this command starts a read operation. the start address of the burst read is determined by the column address (see ?address pins table? in pin function) and the bank select address. after the comple tion of the read operation, all output buffers become high-z. read with auto precharge [reada] this command starts a read operation. after completion of the read operation, precharg e is automatically executed. column address strobe and write command [writ] this command starts a write operation. the start address of the burst write is determined by the column address (see ?address pins table? in pin function) and the bank select address. write with auto precharge [writa] this command starts a write operation. after completion of the write operation, prechar ge is automatically executed.
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 15 row address strobe and bank activate [act] this command activates the bank that is selected by ba0 and ba1 (see bank select signal table) and determines the row address (address pins table in ?pin function?). precharge selected bank [pre] this command starts precharge operation for the bank sele cted by ba0 and ba1. (see bank select signal table) [bank select signal table] ba0 ba1 bank 0 l l bank 1 h l bank 2 l h bank 3 h h remark: h: vih. l: vil. precharge all banks [pall] this command starts a precharge operation for all banks. refresh [ref/self] this command starts a refresh operation. there are two types of refresh oper ation, one is auto -refresh, and another is self-refresh. for details, refe r to the cke truth table section. mode register set/extended mode register set [mrs/emrs] the ddr sdram has the two mode registers, the mode regist er and the extended mode register, to defines how it works. the both mode registers are set th rough the address pins in the mode register set cycle. for details, refer to "mode register and extended mode register set".
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 16 function truth table the following tables show the operations that are perf ormed when each command is issued in each state of the ddr sdram. current state /cs /ras /cas /we address command operation precharging* 1 h desl nop l h h h nop nop l h h l bst illegal* 11 l h l h ba, ca, a10 read/reada illegal* 11 l h l l ba, ca, a10 writ/writa illegal* 11 l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall nop l l l illegal idle* 2 h desl nop l h h h nop nop l h h l bst nop l h l h ba, ca, a10 read/reada illegal* 11 l h l l ba, ca, a10 writ/writa illegal* 11 l l h h ba, ra act activating l l h l ba, a10 pre, pall nop l l l h ref, self refresh/ self-refresh* 12 l l l l mode mrs mode register set* 12 refresh (auto-refresh)* 3 h desl nop l h h h nop nop h h h l bst illegal l h l illegal l l illegal activating* 4 h desl nop l h h h nop nop l h h l bst illegal* 11 l h l h ba, ca, a10 read/reada illegal* 11 l h l l ba, ca, a10 writ/writa illegal* 11 l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall illegal* 11 l l l illegal active* 5 h desl nop l h h h nop nop l h h l bst nop l h l h ba, ca, a10 read/reada starting read operation l h l l ba, ca, a10 writ/writa starting write operation l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall pre-charge l l l illegal
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 17 current state /cs /ras /cas /we address command operation read* 6 h desl nop l h h h nop nop l h h l bst burst stop l h l h ba, ca, a10 read/reada interrupting burst read operation to start new read l h l l ba, ca, a10 writ/writa illegal* 13 l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall interrupting burst read operation to start pre-charge l l l illegal read with auto pre- charge* 7 h desl nop l h h h nop nop l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 14 l h l l ba, ca, a10 writ/writa illegal* 14 l l h h ba, ra act illegal* 11, 14 l l h l ba, a10 pre, pall illegal* 11, 14 l l l illegal write* 8 h desl nop l h h h nop nop l h h l bst burst stop l h l h ba, ca, a10 read/reada interrupting burst write operation to start read operation. l h l l ba, ca, a10 writ/writa interrupting burst write operation to start new write operation. l l h h ba, ra act illegal* 11 l l h l ba, a10 pre, pall interrupting write operation to start pre-charge. l l l illegal write recovering* 9 h desl nop l h h h nop nop l h h l bst illegal l h l h ba, ca, a10 read/reada starting read operation. l h l l ba, ca, a10 writ/writa starting new write operation. l l h h ba, ra act illegal* 11 l l h l ba, a10 pre/pall illegal* 11 l l l illegal
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 18 current state /cs /ras /cas /we address command operation write with auto pre- charge* 1 h desl nop l h h h nop nop l h h l bst illegal l h l h ba, ca, a10 read/reada illegal* 14 l h l l ba, ca, a10 writ/writ a illegal* 14 l l h h ba, ra act illegal* 11, 14 l l h l ba, a10 pre, pall illegal* 11, 14 l l l illegal remark: h: vih. l: vil. : don?t care. notes: 1. the ddr sdram is in "precharging" st ate for trp after precharge command is issued. 2. the ddr sdram reaches "idle" state trp after precharge command is issued. 3. the ddr sdram is in "refresh" state fo r trfc after auto-refresh command is issued. 4. the ddr sdram is in "activating" st ate for trcd after act command is issued. 5. the ddr sdram is in "active" stat e after "activating" is completed. 6. the ddr sdram is in "read" state until burst dat a have been output and dq output circuits are turned off. 7. the ddr sdram is in "read with auto prec harge" from reada command until burst data has been output and dq output circuits are turned off. 8. the ddr sdram is in "write" state from writ command to the last burst data are input. 9. the ddr sdram is in "write recoveri ng" for twr after the last data are input. 10. the ddr sdram is in "write with auto precha rge" until twr after the last data has been input. 11. this command may be issued for other banks, depending on the st ate of the banks. 12. all banks must be in "idle". 13. before executing a write command to stop the pr eceding burst read operati on, bst command must be issued. 14. the ddr sdram supports the concu rrent auto precharge feat ure, a read with auto precharge or a write with auto precharge, can be followed by any command to the other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitat ions apply (e.g. contention between read data and write data must be avoided.) the minimum delay from a read or write command with auto precharge, to a command to a different bank, is summarized below. from command to command (different bank, non- interrupting command) minimum delay (concurrent ap supported) units read w/ap read or read w/ap bl/2 tck write or write w/ap cl (rounded up)+ (bl/2) tck precharge or activate 1 tck write w/ap read or read w/ap 1 + (bl/2) + twtr tck write or write w/ap bl/2 tck precharge or activate 1 tck
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 19 cke truth table cke current state command n ? 1 n /cs /ras /cas /we address notes idle auto-refresh command (ref) h h l l l h 2 idle self-refresh entry (self) h l l l l h 2 h l l h h h active/idle power-down entry (pden) h l h idle deep power-down entry (dpden) h l l h h l l h l h h h self-refresh self-refresh exit (selfx) l h h l h l h h h power-down power-down exit (pdex) l h h deep power-down power-down exit (dpdex) l h notes: 1. h: vih . l: vil : don?t care. 2. all the banks must be in id le before executing this command. 3. the cke level must be kept for 1 clock cycle at least. auto-refresh command [ref] this command executes auto-refresh. the bank and t he row addresses to be refreshed are internally determined by the internal refresh controller. the output buffer bec omes high-z after auto-refresh start. precharge has been completed automatically after the auto-refresh. the act or mrs command can be issued trfc after the last auto- refresh command. the average refresh cycle is 7.8 s. to allow for improved efficiency in scheduling, some flexibility in the absolute refresh interval (64ms) is provided. a maximum of eight auto-refresh commands can be posted to the ddr sdram or the maximum absolute interval between any auto-re fresh command and the next auto-refresh command is 8 tref. self-refresh entry [self] this command starts self-refresh. the self-refresh operation continues as long as cke is held low. during the self- refresh operation, all row addresses ar e repeated refreshing by the internal refresh controller. a self-refresh is terminated by a self-refresh exit command. power-down mode entry [pden] tpden after the cycle when [pden] is issued, the ddr sdram enters into power-down mode. in power-down mode, power consumption is suppressed by deactivating the input initial circuit. power-down mode continues while cke is held low. no internal refresh operation occurs during the power-down mode. deep power-down entry [dpden] after the command execution, deep power-down mo de continues while cke remains low. before executing deep power-down, all bank s must be precharged or in idle state. self-refresh exit [selfx] this command is executed to exit from self-refresh mode. tsrex after [selfx], the device will be into idle state. power-down exit [pdex] the ddr sdram can exit from power-down mode tpdex (1 cycle min.) after the cycle when [pdex] is issued.
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 20 deep power-down exit [dpdex] as cke goes high in the deep power-down mode, the ddr mobile ram exit from the deep power-down mode through deep power-down exiting sequence. simplified state diagram precharge row active idle idle power down auto refresh self refresh mode register set active power down power on writea reada sr entry sr exit mrs refresh cke cke_ cke cke_ active write read bst bst write with ap read with ap power applied precharge ap read write with ap read with read with ap precharge precharge precharge read read write write extended mode register set emrs deep power down dpden deep power down exit sequence automatic sequence manual input deep power down exit sequence
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 21 operation of the ddr sdram initialization the ddr sdram is initialized in the power-on sequence according to the following. 1. provide power, the device core power (vdd) and the device i/o power (vddq) must be brought up simultaneously to prevent device latc h-up. although not required, it is recommended that vdd and vddq are from the same power source. also assert and hol d clock enable (cke) to a lv-cmos logic high level. 2. once the system has established consis tent device power and cke is driven high, it is safe to apply stable clock. 3. there must be at least 200s of va lid clocks before any command may be given to the dram. during this time nop or deselect (desl) commands must be issued on the command bus. 4. issue a precharge all command. 5. provide nops or desl commands for at least trp time. 6. issue an auto-refresh command followed by nops or d esl command for at least trfc time. issue the second auto-refresh command followed by nops or desl comm and for at least trfc time. note as part of the initialization sequence there must be two auto-refresh comm ands issued. the typical flow is to issue them at step 6, but they may also be issued between steps 10 and 11. 7. using the mrs command, load the base mode register. set the desired operating modes. 8. provide nops or desl commands for at least tmrd time. 9. using the mrs command, program the extended mode register for the desired operating modes. 10. provide nop or desl commands for at least tmrd time. 11. the dram has been properly initialized and is ready for any valid command.
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 22 mode register and extended mode register set there are two mode registers, the m ode register and the extended mode regi ster so as to define the operating mode. parameters are set to both through the a0 to the a13 and ba0 and ba1 pins by the mode register set command [mrs] or the extended mode register set co mmand [emrs]. the mode regi ster and the extended mode register are set by inputting signal via the a0 to the a13 and ba0 and ba1 pins during mode register set cycles. ba0 and ba1 determine which one of the mode register or the extended mode regist er are set. prior to a read or a write operation, the mode register must be set. mode register the mode register has four fields; reserved : a13 through a7 /cas latency : a6 through a4 burst type : a3 burst length : a2 through a0 following mode register programming, no command can be issued before at least 2 clocks have elapsed. /cas latency /cas latency must be set to 3. burst length burst length is the number of words that will be output or input in a read or write cycle. after a read burst is completed, the output bus will become high-z. t he burst length is programmable as 2, 4, 8 and 16. burst type (burst sequence) the burst type specifies the order in which the burst data will be addressed. this order is programmable as either ?sequential? or ?interleave?. ?burst operation? shows the addressing sequenc e for each burst length for each burst type. a2 a1 a0 burst length 001 2 0 0 0 reserved bt = 0 bt = 1 100 16 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved 010 4 011 8 2 reserved 16 reserved reserved reserved 4 8 a3 0 sequential 1 interleave burst type a6 a5 a4 cas latency 0 0 0 reserved reserved reserved 001 010 3 011 1 0 0 reserved reserved 101 110 reserved reserved 111 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 00 0 0 0 lmode bt bl a11 0 a12 0 a13 a10 ba1 0 ba0 0 mrs mode register set
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 23 extended mode register the extended mode register is as follows; reserved : a13 through a7, a4, a3 driver strength : a6 through a5 partial array self-refresh : a2 through a0 following extended mode register progr amming, no command can be issued befor e at least 2 clocks have elapsed. driver strength by setting specific parameter on a6 and a5, drivin g capability of data output drivers is selected. auto temperature compensated self-refresh (atcsr) the ddr mobile ram automatically changes the self-refr esh cycle by on die temperature sensor. no extended mode register program is required. manual tcsr (tem perature compensated self-ref resh) is not implemented. partial array self-refresh memory array size to be refreshed during self-refresh opera tion is programmable in order to reduce power. data outside the defined area will not be retained during self-refresh. deep power-down exit sequence in order to exit from the deep power-down mode and ente r into the idle mode, the following sequence is needed, which is similar to the power-on sequence. (1) a 200 s or longer pause must precede any command other than ignore command (desl). (2) after the pause, all banks must be precharged usin g the precharge command (the precharge all banks command is convenient). (3) once the precharge is completed and the minimum trp is satisfied, two or more auto-refresh must be performed. (4) both the mode register and the extended mode register must be programmed. after the mode register set cycle or the extended mode register set cycle, tm rd (2 clocks minimum) pause must be satisfied. remarks: 1 the sequence of auto-refresh, mode register program ming and extended mode register programming above may be transposed. 2 cke must be held high. a5 normal 1/2 strength 1/4 strength 1/8 strength a6 0 0 1 1 0 1 0 1 driver strength a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 00 0 ds 00 pasr a1 all banks bank0 & bank1 (ba1 = 0) bank0 (ba = ba1 = 0) reserved reserved reserved reserved reserved a2 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 a0 0 1 0 1 0 1 0 1 refresh array a11 a10 ba0 0 ba1 10 a12 0 a13 0 extended mode register set
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 24 power-down mode and cke control ddr sdram will be into power-down mode at the second ck rising edge after cke to be low level with nop or desl command at first ck rising ed ge after cke signal to be low. ck /ck cke address power-down mode command nop valid* 2 nop nop valid* 1 valid* 2 valid* 1 notes: 1. valid* 1 can be either activate command or precharge command, when valid* 1 is activate command, power-down mode will be active power-down mode, while it will be precharge power down mode, if valid* 1 will be precharge command. 2. valid* 2 can be any command as long as all of specified ac parameters are satisfied. power-down entry and exit however, if the cke has one clock cycle high and on clock cycle low just as below, even ddr sdram will not enter power-down mode, this command flow does not hurt any data and can be done. ck /ck cke command act nop nop pre note: assume pre and act command is closing and activating same bank. cke control
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 25 burst operation the burst type (bt) and the first three bits of t he column address determine the order of a data out. a2 a1 a0 addressing(decimal) 00 0 00 1 01 0 01 1 11 1 interleave sequence 10 0 11 0 10 1 starting ad. 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 2, 3, 4, 5, 6, 7, 3, 4, 5, 6, 7, 4, 5, 6, 7, 5, 6, 7, 6, 7, 7, 0 0, 1 0, 1, 2 0, 1, 2, 3 0, 1, 2, 3, 4 0, 1, 2, 3, 4, 5 0, 1, 2, 3, 4, 5, 6 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 2, 3, 0, 1, 6, 7, 3, 2, 1, 0, 7, 4, 5, 6, 7, 5, 4, 7, 6, 7, 7, 6 4, 5 6, 5, 4 0, 1, 2, 3 6, 1, 0, 3, 2 4, 5, 2, 3, 0, 1 6, 5, 4, 3, 2, 1, 0 burst length = 8 a2 a1 a0 addressing(decimal) interleave sequence a3 starting ad. 1 1 1 1 15, 14 13, 12, 11, 10, 9, 8, 7, 0, 1, 2, 3, 4, 5, 6, 15, 6, 7, 5, 4, 3, 2, 1, 0 14, 13, 12, 11, 10, 9, 8, 0 1019, 8 7, 6, 5, 4, 3, 2, 1, 10, 11, 12, 13, 14, 15, 0, 9, 0, 1, 3, 2, 5, 4, 7, 6 8, 11, 10, 13, 12, 15, 14, 0 1 1 1 11, 10 9, 8, 7, 6, 5, 4, 3, 12, 13, 14, 15, 0, 1, 2, 11, 2, 3, 1, 0, 7, 6, 5, 4 10, 9, 8, 15, 14, 13, 12, 0 1 1 0 10, 9 8, 7, 6, 5, 4, 3, 2, 11, 12, 13, 14, 15, 0, 1, 10, 3, 2, 0, 1, 6, 7, 4, 5 11, 8, 9, 14, 15, 12, 13, 0 1008, 7 6, 5, 4, 3, 2, 1, 0, 9, 10, 11, 12, 13, 14, 15, 8, 1, 0, 2, 3, 4, 5, 6, 7 9, 10, 11, 12, 13, 14, 15, 1 1 0 1 13, 12 11, 10, 9, 8, 7, 6, 5, 14, 15, 0, 1, 2, 3, 4, 13, 4, 5, 7, 6, 1, 0, 3, 2 12, 15, 14, 9, 8, 11, 10, 1 1 0 0 12, 11 10, 9, 8, 7, 6, 5, 4, 13, 14, 15, 0, 1, 2, 3, 12, 5, 4, 6, 7, 0, 1, 2, 3 13, 14, 15, 8, 9, 10, 11, 1 1 1 0 14, 13 12, 11, 10, 9, 8, 7, 6, 15, 0, 1, 2, 3, 4, 5, 14, 7, 6, 4, 5, 2, 3, 0, 1 15, 12, 13, 10, 11, 8, 9, 00 0 00, 15 14, 13, 12, 11, 10, 9, 8, 1, 2, 3, 4, 5, 6, 7, 0, 9, 8, 10, 11, 12, 13, 14, 15 1, 2, 3, 4, 5, 6, 7, 10 0 04, 3 2, 1, 0, 15, 14, 13, 12, 5, 6, 7, 8, 9, 10, 11, 4, 13, 12, 14, 15, 8, 9, 10, 11 5, 6, 7, 0, 1, 2, 3, 00 1 01, 0 15, 14, 13, 12, 11, 10, 9, 2, 3, 4, 5, 6, 7, 8, 1, 8, 9, 11, 10, 13, 12, 15, 14 0, 3, 2, 5, 4, 7, 6, 01 1 03, 2 1, 0, 15, 14, 13, 12, 11, 4, 5, 6, 7, 8, 9, 10, 3, 10, 11, 9, 8, 15, 14, 13, 12 2, 1, 0, 7, 6, 5, 4, 01 0 02, 1 0, 15, 14, 13, 12, 11, 10, 3, 4, 5, 6, 7, 8, 9, 2, 11, 10, 8, 9, 14, 15, 12, 13 3, 0, 1, 6, 7, 4, 5, 11 0 06, 5 4, 3, 2, 1, 0, 15, 14, 7, 8, 9, 10, 11, 12, 13, 6, 15, 14, 12, 13, 10, 11, 8, 9 7, 4, 5, 2, 3, 0, 1, 1 0015, 4 3, 2, 1, 0, 15, 14, 13, 6, 7, 8, 9, 10, 11, 12, 5, 12, 13, 15, 14, 9, 8, 11, 10 4, 7, 6, 1, 0, 3, 2, 11 1 07, 6 5, 4, 3, 2, 1, 0, 15, 8, 9, 10, 11, 12, 13, 14, 7, 14, 15, 13, 12, 11, 10, 9, 8 6, 5, 4, 3, 2, 1, 0, burst length = 16 a1 a0 addressing(decimal) 00 01 10 11 interleave sequence starting ad. 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 burst length = 4 a0 addressing(decimal) 0 1 interleave sequence starting ad. 0, 1 1, 0 0, 1 1, 0 burst length = 2
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 26 read/write operations bank active a read or a write operation begins with the bank active command [act]. the bank active command determines a bank address and a row address. for the bank and the row, a read or a write command can be issued trcd after the act is issued. read operation the burst length (bl), the /cas latency (cl) and the burst type (bt) of the mode register are referred when a read command is issued. the burst length (bl) determines the length of a sequent ial output data by the read command that can be set to 2, 4, 8 or 16. t he starting address of the burst read is def ined by the column address, the bank select address (see ?pin function?) in the cycle when the read command is issued. the data output timing is characterized by cl and tac. the read burst start (cl-1) tck + tac (ns) after the clock rising edge where the read command is latched. the ddr sdram out puts the data strobe throu gh dqs pins simultaneously with data. trpre prior to the first rising edge of the data strobe, the dqs pins are driven low fr om high-z state. this low period of dqs is referred as read preamble. the burst data are output coinci dentally at both the rising and falling edge of the data strobe. the dq pins become high-z in the next cycl e after the burst read operation completed. trpst from the last falling edge of the dat a strobe, the dqs pins become high-z. th is low period of dqs is referred as read postamble. out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 ck /ck address dqs dq bl = 2 bl = 4 bl = 8 command cl = 3 bl: burst length trcd trpst act nop nop nop read row column out0 out1 out2 out3 out4 out5 out6 out7 out 14 out 15 bl = 16 trpre read operation (burst length)
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 27 ck /ck vtt vtt dqs dq command t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 out0 out1 out2 out3 tac,tdqsck read nop trpre trpst read operation (/cas latency) write operation the burst length (bl) and the burst type (bt) of the mode register are referr ed when a write command is issued. the burst length (bl) determines the length of a sequential dat a input by the write command t hat can be set to 2, 4,8 or 16. the latency from write command to data input is fix ed to 1. the starting address of the burst write is defined by the column address, the bank select address (see ?pin function?) in the cycle when the write command is issued. dqs should be input as the strobe for the input-data and dm as well during burst operation. twpre prior to the first rising edge of dqs, dqs must be set to low. twpst afte r the last falling edge of dqs, the dqs pins can be changed to high-z. the leading low period of dqs is refe rred as write preamble. the last low period of dqs is referred as write postamble. in1 in0 in1 in2 in3 in0 in1 in2 in3 in4 in5 in6 in7 ck /ck address dqs dq bl = 2 bl = 4 bl = 8 command bl: burst length in0 act nop nop nop writ twpre row column trcd twpst in0 in1 in2 in3 in4 in5 in6 in7 in 14 in 15 bl = 16 write operation
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 28 burst stop burst stop command during burst operation the burst stop (bst) command stops the burst read and sets all output buffers to high-z. tbstz (= cl) cycles after a bst command issued, all dq and dqs pins become high-z. the bst command is also supported for the burst write oper ation. no data will be written in subsequent cycles. note that bank address is not refe rred when this command is executed. ck /ck dqs dq command t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 out0 out1 cl: /cas latency read bst nop tbstz burst stop during a read operation
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 29 auto precharge read with auto precharge the precharge is automatically performed after completing a read operation. the precharge starts bl/2 (= trpd) clocks after reada command input. tras lock out mechanism for reada allows a read command with auto precharge to be issued to a bank that has been activa ted (opened) but has not yet satisfied the tras (min) specification. a column command to the other active bank can be issued the next cycle after the last data output. read with auto precharge command does not limit row commands execution for other bank. out0 out1 out2 out3 ck /ck dq command trp (min) trcd (min) act note: internal auto-precharge starts at the timing indicated by " ". nop bl/2 (= trpd) reada act dqs tac,tdqsck tras (min) read with auto precharge write with auto precharge the precharge is automatically performed after completing a burst write operation. the precharge operation is started write latency (wl) + bl/2 + twr (= twpd) clocks after writa command issued. a column command to the other banks can be issued the ne xt cycle after the internal precharge command issued. write with auto precharge command does not limit row commands execution for other bank. in1 in2 in3 in4 ck /ck dq command dm tras (min) trcd (min) trp dqs act writa act wl + bl/2 + twr (= twpd) note: internal auto-precharge starts at the timing indicated by " ". bl = 4 nop nop burst write (bl = 4)
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 30 command intervals a read command to the consecutive read command interval destination row of the consecutive read command bank address row address state operation 1. same same active the consecutive read can be performed afte r an interval of no less than 1 cycle to interrupt the preceding read operation. 2. same different ? precharge the bank to interrupt the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be iss ued. see ?a read command to the consecutive precharge interval? section. 3. different any active the consecutive read can be performed afte r an interval of no less than 1 cycle to interrupt the preceding read operation. idle precharge the bank without interrupting the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. out a0 out a1 out b0 out b1 out b2 out b3 ck /ck address ba dq dqs command tn t0 tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 bank0 active cl = 3 bl = 4 bank0 nop act nop read row read column = a read column = b read column = a dout column = b dout column a column b read to read command interval (same row address in the same bank)* note: n 4
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 31 out a0 out a1 out b0 out b1 out b3 ck /ck address ba dq dqs command t1 t0 t2 bank0 active bank3 active bank0 read bank3 read cl = 3 bl = 4 nop act nop nop row0 act read row1 column a read column b column = a read column = b read bank3 dout bank0 dout out b2 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 read to read command interval (different bank)* note: n 4
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 32 a write command to the consecutive write command interval destination row of the consecutive write command bank address row address state operation 1. same same active the consecutive write can be performed afte r an interval of no less than 1 cycle to interrupt the preceding write operation. 2. same different ? precharge the bank to interrupt the preceding write operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be iss ued. see ?a write command to the consecutive precharge interval? section. 3. different any active the consecutive write can be performed afte r an interval of no less than 1 cycle to interrupt the preceding write operation. idle precharge the bank without interrupting the preceding write operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. ina0 ina1 inb0 inb1 inb2 inb3 ck /ck address ba dq command t0 tn+1 tn tn+2 tn+3 tn+4 tn+5 tn+6 bank0 active bl = 4 bank0 nop dqs act nop writ row column a writ column b column = a write column = b write write to write command interval (same row address in the same bank)
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 33 ina0 ina1 inb0 inb1 inb2 inb3 ck /ck address ba dq command t1 t0 t2 tn tn+1 tn+2 tn+3 tn+4 tn+5 bank0 active bank3 active bank0 write bank3 write bl = 4 bank0, 3 nop dqs act nop act row0 row1 column a nop writ column b writ write to write command interval (different bank)
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 34 a read command to the consecutive write command interval with the bst command destination row of the consecutive write command bank address row address state operation 1. same same active issue the bst command. tbstw ( tbstz) after the bst command, the consecutive write command can be issued. 2. same different ? precharge the bank to interrupt the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be i ssued. see ?a read command to the consecutive precharge interval? section. 3. different any active issue the bst command. tbstw ( tbstz) after the bst command, the consecutive write command can be issued. idle precharge the bank independently of the preceding read operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive write command can be issued. out0 out1 in0 in1 in2 in3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl = 3 dqs output input tbstw ( tbstz) high-z read writ bst nop nop tbstz (= cl) read to write command interval
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 35 a write command to the consecutive read command interval: to complete the burst operation destination row of the consecutive read command bank address row address state operation 1. same same active to complete the burst operation, the consecutive read command should be performed twrd after the write command. 2. same different ? precharge the bank twpd after the preceding write command. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be i ssued. see ?a read command to the consecutive precharge interval? section. 3. different any active to complete a burst operation, the consecutive read command should be performed twrd after the write command. idle precharge the bank independently of the preceding write operation. trp after the precharge command, issue the act command. trcd after the act command, the consecutive read command can be issued. in0 in1 in2 in3 out2 out0 out1 ck /ck dm dq command t1 t0 t2 t3 tn tn + 1 tn + 2 tn + 3 tn + 4 bl = 4 cl = 3 twrd (min) dqs input output writ nop nop read twtr* note: twtr is referenced from the first positive ck edge after the last desired data in pair twtr. write to read command interval
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 36 a write command to the consecutive read command interval: to interrupt the write operation destination row of the consecutive read command bank address row address state operation 1. same same active dm must be input 1 cycle prior to the read command input to prevent from being written invalid data. in case, the read command is input in the next cycle of the write command, dm is not necessary. 2. same different ? ?* 1 3. different any active dm must be input 1 cycle prior to the read command input to prevent from being written invalid data. in case, the read command is input in the next cycle of the write command, dm is not necessary. idle ?* 1 note: 1. precharge must be preceded to read command. therefore read command ca n not interrupt the write operation in this case. write to read command interval (same bank, same row address) in0 in1 in2 out0 out1 out3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl = 3 dqs data masked read nop writ high-z high-z out2 [write to read delay = 1 clock cycle]
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 37 in0 in1 in2 in3 out1 out2 out3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 t8 bl = 4 cl = 3 dqs data masked read nop nop writ high-z high-z out0 [write to read delay = 2 clock cycle] in0 in1 in2 in3 out0 out1 ck /ck dm dq command bl = 4 cl = 3 dqs data masked read writ nop nop twtr* note: twtr is referenced from the first positive ck edge after the last desired data in pair twtr. out2 out3 t1 t0 t2 t3 t4 t5 t6 t7 t8 t9 [write to read delay = 4 clock cycle]
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 38 a write command to the bust stop command interval: to interrupt the write operation write to bst command interval (same bank, same row address) in0 in1 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 bl = 4 or longer dqs data will be written bst nop writ following data will not be written. [write to bst delay = 1 clock cycle] in0 in1 in2 in3 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 bl = 8 or longer dqs bst nop nop writ data will be written following data will not be written. [write to bst delay = 2 clock cycle]
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 39 in0 in1 in2 in3 in4 in5 ck /ck dm dq command t1 t0 t2 t3 t4 t5 t6 t7 bl = 8 or longer dqs bst writ nop nop data will be written following data will not be written. [write to bst delay = 3 clock cycle]
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 40 a read command to the consecutive precharge command interval operation by each case of destination ba nk of the consecutive precharge command. bank address operation 1. same the pre and pall command can interrupt a read operation. to complete a burst read operation, trpd is required between the read and the precharge command. please refer to the following timing chart. 2. different the pre command does not interrupt a read command. no interval timing is required betwe en the read and the precharge command. read to precharge command interval (same bank) : to output all data to complete a burst read operation and get a burst length of data, the consecutive pr echarge command must be issued trpd (= bl/ 2 cycles) after the read command is issued. ck /ck dq dqs command t1 t0 t2 t3 t4 t5 t6 t7 t8 trpd = bl/2 nop nop nop pre/ pall out0 out1 out2 out3 read read to precharge command interval (same bank): to output all data (cl = 3, bl = 4) read to precharge command interval (same bank): to stop output data a burst data output can be in terrupted with a precharge command. all dq pins and dqs pins become high-z thzp (= cl) after the precharge command. out0 ck /ck dq dqs command t1 t0 t2 t3 t4 t5 t6 t7 t8 high-z high-z thzp read nop nop pre/pall out1 read to precharge command interval (same bank): to stop output data (cl = 3, bl = 4, 8)
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 41 a write command to the consecutive precharge command interval (same bank) operation by each case of destination ba nk of the consecutive precharge command. bank address operation 1. same the pre and pall command can interrupt a write operation. to complete a burst write operation, twpd is required between the write and the precharge command. please refer to the following timing chart. 2. different the pre command does not interrupt a write command. no interval timing is required between the write and the precharge command. write to precharge command interval (same bank) the minimum interval twpd is necessary between the write command and the precharge command. in0 in1 in2 in3 ck /ck dq dm dqs command t1 t0 t2 t3 t4 tn tn + 1 tn + 2 last data input twpd writ nop nop twr pre/pall write to precharge command interval (same bank) (bl = 4)
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 42 in0 in1 in2 in3 ck /ck dq dqs command t1 t0 t2 t3 tn tn + 1 tn + 2 tn + 3 last data input twpd writ nop nop twr pre/pall dm data masked bl = 4 write to precharge command interval (same bank) (bl = 4, dm to mask data)
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 43 bank active command interval destination row of the consecutive act command bank address row address state operation 1. same any active two successive act commands can be issued at trc interval. in between two successive act operations, precharge command should be executed. 2. different any active precharge the bank. trp after the precharge command, the consecutive act command can be issued. idle trrd after an act command, the next act command can be issued. ck /ck command ba trc address actv trrd bank0 active bank3 active bank0 precharge bank0 active pre act row: 0 nop nop nop act act row: 1 row: 0 bank active to bank active mode register set to bank-active command interval the interval between setting the mode register and ex ecuting a bank-active command must be no less than tmrd. ck /ck command address nop nop mrs act tmrd mode register set bank3 active code bs and row mode register set to bank active
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 44 dm control dm can mask input data. by setting dm to low, data ca n be written. udm and ldm can mask the upper and lower byte of input data, respectively. when dm is set to high, the corresponding data is not written, and the previous data is held. the latency between dm input and enabling/disabling mask function is 0. dq dqs t1 t2 t3 t4 t5 t6 dm write mask latency = 0 mask mask dm control
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 45 timing waveforms command and addresses input timing definition ck /ck command (/ras, /cas, /we, /cs) address tis tis tih tih = don't care read timing definition (1) ck /ck command dq (output) dqs high-z high-z high-z high-z read tlz (min.) thz (max.) cl = 3 bl = 2 tlz (min.)
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 46 read timing definition (2) tdqsck tdqsck tdsc tac (min.) tac (max.) tdqsq tdqsq tqh tqh tqhs /ck ck fastest dq (output) dqs slowest dq (output) data valid window fastest dq (output) dqs slowest dq (output) data valid window bl = 4 = invalid tac (min.) tac (max.) write timing definition /ck ck dqs dm dq (din) tds tdh tdqss twpre twpres tds tdh tck tdsh tdss tdss tdqsl tdqsh tdipw tdipw tdipw twpst tdsc = don't care bl = 4
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 47 initialize sequence ck /ck cke vdd vddq /cs /ras /cas /we ba1 a10 address dm dq, dqs h igh -z tmrd address key 2 refresh cycles are necessary precharge all banks command is necessary vdd/vddq powered up clock stable mode register set command is necessary extended mode register set command is necessary auto-refresh command is necessary activate command auto-refresh command is necessary ba0 clock cycle is necessary vih = don't care address key trfc trfc trp tck 200 s tmrd
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 48 read cycle bank 0 active bank 0 read bank 0 precharge cl = 3 bl = 4 bank0 access = don't care bank 0 active bank 0 read bank 0 precharge tis tih tch tck tcl tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih /ras a10 address high-z high-z /cs cke ck /ck /cas /we ba dqs (output) dq (output) dm vih trcd tras trp trc trpst trpre tdsc
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 49 write cycle bank 0 active cl = 2 bl = 4 bank0 access = don't care bank 0 active bank 0 write bank 0 precharge tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih tis tih vih trcd tras trc trp twr /cs ck /ck cke /ras /cas /we ba a10 address dq (input) dm dqs (input) tck tch tcl tds tds tds tdh tdh tdh tdqsl twpst tdqss tdqsh
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 50 mode register set cycle t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 /ck ck cke /cs /ras /cas /we ba address dm dq b valid code code trp precharge if needed mode register set bank 3 active bank 3 read r: b c: b vih bank 3 precharge tmrd high-z high-z cl = 3 bl = 4 = don't care dqs read/write cycle r:a c:a c:b r:b c:b'' b?? bank 0 active bank 3 active bank 0 read bank 3 read t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 tn tn+1 tn+2 tn+3 tn+4 cke /ras /cs dqs /cas /we address ck ba dq /ck bank 3 write twrd vih trwd b read cycle cl = 3 bl = 4 = don't care dm a write read read
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 51 auto-refresh cycle precharge if needed auto refresh bank 0 active bank 0 read /ck ck cke /cs /cas /we ba address dm dq /ras cl = 3 bl = 4 = don't care vih trp a10=1 r: b c: b b trfc dqs high-z high-z
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 52 self-refresh cycle self refresh entry self refresh exit /ck cke /cs /ras /cas /we ba address dm dq ck precharge if needed bank 0 active bank 0 read trp tsrex a10=1 r: b c: b dqs bl = 4 = don't care tis tih cke = low
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 53 power-down entry and exit a10=1 r: c r: b /ck cke /cs /ras /cas /we ba address dm dq dqs ck precharge if needed power down entry power down exit bank 0 active bank 0 read tpdex bl = 4 = don't care tpden cke = low trp t is t ih tcke
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 54 deep power-down entry cke /cs /ras /cas /we ba0 a10 address dm dq ba1 t0 t1 t2 t3 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 high-z precharge all banks command deep power down entry ck /ck trp = don't care
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 55 deep power-down exit* cke /cs /ras /cas /we ba1 a10 address dm dq high-z tmrd tmrd address key address key 2 refresh cycles are necessary trfc trfc precharge all banks command is necessary deep power down exit command mode register set command is necessary extended mode register set command is necessary cbr (auto) refresh command is necessary activate command cbr (auto) refresh command is necessary ba0 clock cycle is necessary ck /ck trp 200 s vih = don't care note: the sequence of auto-refresh, mode register pr ogramming and extended mode register programming above may be transposed.
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 56 package drawing 60-ball fbga solder ball: lead free (sn-ag-cu) 11.0 0.1 1.6 11.5 0.1 1.0 max a b 6.4 0.8 0.4 7.2 index mark 0.8 0.2 s a 0.2 s b 0.2 s 0.1 s s 60- 0.45 0.05 0.08 m sa b eca-ts2-0229-01 0.35 0.05 unit: mm index mark
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 57 recommended soldering conditions please consult with our sales offices for soldering conditions of the edd10163abh. type of surface mount device edd10163abh: 60-ball fbga < lead free (sn-ag-cu) >
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 58 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
edd10163abh-ls preliminary data sheet e1379e20 (ver. 2.0) 59 m01e0706 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] be aware that this product is for use in typical electronic equipment for general-purpose applications. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, users are instructed to contact elpida memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] usage in environments with special characteristics as listed below was not considered in the design. accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. example: 1) usage in liquids, including water, oils, chemicals and organic solvents. 2) usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) usage involving exposure to significant amounts of corrosive gas, including sea air, cl 2 , h 2 s, nh 3 , so 2 , and no x . 4) usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) usage in places where dew forms. 6) usage in environments with mechanical vibration, impact, or stress. 7) usage near heating elements, igniters, or flammable items. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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